High Speed Probabilistic Adder for signal Processing Subsystems

This study proposes a new high performance and low power adder using new design style called probabilistic is proposed. The design of a probabilistic adder that achieves low power and high speed operation. The delay and power dissipation are reduced by dividing the adder into two parts to reduce the carry chain. This dividing approach reduces active power by minimizing extraneous glitches and transitions. It is an approach for the design and comparison of 16-bit adders for low-power signal processing applications. Simulation and Synthesis results show that the proposed adder outperforms the conventional adders in terms of power consumption, delay and transistor count.